1. Technical Field
The present invention relates to a data filtering technology.
2. Background Arts
In image processing, etc., there is a case of separating spatial frequencies on a whole image plane into low frequency components and high frequency component in order to remarkably improve visual recognizability of a displayed image. Then, a known technology is, for example, such that the low frequency components are restrained and thus synthesized with the high frequency components, and a dynamic range, with contrasts in minutes portions kept, is compressed, and so forth.
The separation into the low frequency components in such a case involves using, generally, a moving average. The moving average is a process of obtaining an average of, e.g., (2n+1)×(2n+1) matrix with respect to all pixels given by Np×Np. Herein, 2n+1 is an odd number equal to or smaller than Np.
FIG. 1 shows a processing example of a mean filter. As shown in FIG. 1, in the mean filter, a mean value of a pixel density value of a target pixel M and pixel density values of pixels peripheral to the target pixel M, is set as a new density value of the target pixel M. When selecting, e.g., n=2, 25 pieces of pixel data (A, B, . . . , Y) disposed in bilateral and vertical directions of the pixel M are added, and an added value is divided by 25, thereby acquiring the pixel M subjected to the filtering process.
FIGS. 2 through 5 show a method of configuring a conventional mean filter. This type of mean filter is configured softwarewise or hardwarewise.
(1) Softwarewise Configuration
FIG. 2 shows an example of configuring the mean filter softwarewise. This mean filter includes a frame memory 302 for retaining input image data, a DSP (Digital Signal processor) 301 for processing the input image data by executing the software, and a calculation memory 303 for calculation of the DSP.
In the case of configuring the mean filter by the software on the DSP 301, the (5×5) pixels such as A, B, . . . , Y shown in FIG. 1 are read from the input image data stored on the frame memory sequentially on a pixel-by-pixel basis into the DSP 301. Then, a mean value of the matrix is calculated by a processing flow as in FIG. 3 by use of the calculation memory 303.
In FIG. 3, the pixel data are read pixel by pixel and sequentially added to a total sum (S). This process is repeated for the pixels A through Y, and the value is divided by 25. In this process, the processing of the (5×5) matrix requires totally 28 steps such as initialization (1 step) of the total sum (S), additions (25 steps) of the pixels A through Y, division (1 step) of the total sum (S) by 25 and the output (1 step) from the calculation memory.
Now, supposing that a clock per pixel on an unillustrated display device is set to 25 MHz, realtime processing of each pixel is required to be done at 700 MHz given by 25 MHz×28=700 MHz, or higher even when each step is processed at 1 clock.
(2) Hardwarewise Configuration
(2-1) Case of Fixed Filter Size
In the case of configuring the mean filter hardwarewise, it is required that the (5×5) matrix peripheral to each pixel be formed with respect to each of the pixels (e.g., 640×480 pixels) of the input image data. For calculating a total value of this (5×5) matrix for every pixel needs to adjust timing (a phase) for addition.
For example, as shown in FIG. 1, when adding the (5×5) matrix peripheral to the pixel M, the phases (the addition timing) of pieces of pixel data A, B, . . . , X are required to be adjusted to a position of the pixel data Y.
Now, as shown in FIG. 1, the lateral direction on the image plane on the image data is called a pixel direction, and the vertical direction is called a line direction. The pixel direction is a direction of moving with the clock on the pixel-by-pixel basis. Further, the line direction is a direction of moving along the line (one row consisting of, e.g., 640 pieces of pixels) perpendicular to the pixel direction. Note that the line is also referred to as the row.
To start with, a discussion on the fifth line (pieces of pixel data U through Y) is made. Respective pieces of pixel data on the fifth line are in the same line as the pixel data Y exists. Hence, there is no necessity of line-delaying respective pieces of pixel data in the fifth line with respect to the pixel data Y. Therefore, the pixel data U is delayed by 4 clocks, the pixel data V is delayed by 3 clocks, the pixel data W is delayed by 2 clocks, and the pixel data X is delayed by 1 clock. The delay of the pixel data may involve using, e.g., a FF (flip-flop). The phases of pieces of pixel data are thereby adjusted to the position of the pixel data Y. A total value of the fifth line is obtained by adding the thus-phase-adjusted pixel data.
Next, the input image data is delayed by 1 line (e.g., 640 pixels) by use of the line memory, and the line of the pixel data P through T is adjusted to the position of the fifth line. Then, the phases of the pixel data P through T are adjusted to the position of the data Y, thereby calculating a total value of the pixel data P through T. Thus, the input image data are sequentially delayed line by line, thus delaying the respective lines up to the fifth line. Then, the pixel data are added in adjustment with the position of the pixel Y by use of the FF. Through this processing, the total value of each line is obtained. Then, the total values of the respective lines are sequentially added, thereby acquiring a total value of the 25 pixels. Moreover, this total value is divided by 25, thereby configuring the mean filter.
FIG. 4 shows a configuration of the mean filter having a (5×5) filter size based on such a circuit. This mean filter circuit includes line memories 311 through 314 for causing delays in the line direction, pixel-directional calculation units 320 through 324 for executing the 5-pixel additions on a line-by-line basis, adders 361 through 365 for sequentially adding the added data of the respective lines, and a multiplier 365 for executing the division by 25 (multiplication by 1/25).
An interior of the pixel-directional calculation unit 320 is constructed of FFs 331 through 334 and adders 341 through 344. The FFs 331 through 334 cause 1-clock delays of the pixel data such as U, V, W, X to be inputted in sequence. Thus, for example, phases of five pieces of pixel data U, V, W, X, Y in the fifth line (containing U, V, W, X, Y) shown in FIG. 1 can be adjusted, and an addable state occurs. In the configuration in FIG. 4, these pieces of pixel data are added by the adders 341 through 344.
The line memories 311 through 314 receive a sequential input of 1-pixel data at 1 clock and are thus stored with 1-line data. Herein, an assumption for facilitating comprehension is that one line consists of, e.g., 640 pixels. Then, the line memory 311 is stored with the data for 1 line (which is called a line L1) at the first 640 clocks. At this time, each piece of the pixel data of the line L1 has a 5-pixel addition by the pixel-directional calculation unit 320, however, this addition is out of phase and is therefore discarded.
Further, at the next 640 clocks, the pixel data of a next line (which is called a line L2) are stored on the line memory 311. At this time, each piece of data of the line L2 has a 5-pixel addition by the pixel-directional calculation unit 320, however, this addition is out of phase and is therefore discarded. Moreover, the data of the line L1 are stored on the line memory 312. At this time, each piece of data of the line L1 has a 5-pixel addition by the pixel-directional calculation unit 321, however, this addition is likewise out of phase and is therefore discarded.
With repetitions of such processing, there occurs a state wherein the pixel data of the first line L1 are stored on the line memory 314, the pixel data of the next line L2 are stored on the line memory 313, the pixel data of the further next line L3 are stored on the line memory 312, and the pixel data of the yet further next line L4 are stored on the line memory 311.
In this state, from the next clocks, the pixel data of the next line L5 are inputted as an input image to the pixel-directional calculation unit 320. Moreover, the pixel data of the lines L4 through L1 are inputted to the pixel-directional calculation units 321 through 324, respectively.
With this processing, it follows that each piece of pixel data of the 5 lines has the 5-pixel addition in the pixel direction in the same phase by the pixel-directional calculation units 320 through 324. Furthermore, the output (the pixel data of each pixel that is replaced with the data integrated by every 5 pixels in the pixel direction) of each of the pixel-directional calculation units 320 through 324 has 5-line integration in the line direction by the adders 361 through 364. The (5×5) pixel data are thereby integrated in the pixel direction and in the line direction, and the integrated result is inputted to the multiplier 365. The multiplier 365 divides this integrated result by 25, thereby outputting a mean value of the 25 pixels.
As in FIG. 4, the (5×5) mean filter needs 20 pieces of FFs, 24 pieces of adders and one piece of multiplier.
FIG. 5 shows a configuration generalized into an (N×N) mean filter. As illustrated in FIG. 5, pieces of hardware for actualizing the (N×N) mean filter are [N−1] systems of line memories for delaying the image data line by line, [(N−1)×N] pieces of FFs, [(N×N)−1] pieces of adders, and one piece of multiplier.
(2-2) Case of Variable Filter Size
FIG. 6 shows a mean filter circuit having a variable filter size (3×3 through N×N). As in FIG. 6, when the filter size is variable from 3×3 to N×N, a configuration having the maximum filter size “N×N” is always prepared as a circuit configuration (the FFs, the line memories and the adders).
Then, the FF outputs of the configuration corresponding to the designated filter size are selected from the total values of the respective lines, and the added values are obtained, thereby enabling the mean filter having the arbitrary filter size to be configured.
For this selection of the FF outputs, the filter circuit in FIG. 6 includes selectors 370, 371, etc. For instance, the selector 371 is a circuit for selecting an arbitrary number (3 through N) of added values in the pixel-directional calculation unit 320. A switching signal 381 designates how many added values are selected. Other pixel-directional calculation units 321, 322, . . . have the same construction.
Moreover, the selector 370 is a circuit for selecting the added result of an arbitrary number of lines among within the line-directional adders, 361, . . . , to which the output of the pixel-direction calculation unit 320, etc. is further added. A switching signal 380 designates the selection of the number of additions in the line direction.